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Realization of spin-wave logic gates
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10.1063/1.2834714
/content/aip/journal/apl/92/2/10.1063/1.2834714
http://aip.metastore.ingenta.com/content/aip/journal/apl/92/2/10.1063/1.2834714
View: Figures

Figures

Image of FIG. 1.
FIG. 1.

XNOR gate. (a) Inserted phase vs current for the current controlled spin wave phase shifters (CPSs) used to construct the XNOR gate prototype. It is clearly visible that the phase shifts in both arms (channels) are identical. The inset shows the phase shifter geometry. (b) Spin-wave XNOR gate geometry. The currents and represent the logical inputs ( corresponds to 0, corresponds to 1), the spin-wave interference signal represents the logical output. Inset: truth table for a XNOR gate. (c) Gate output signals for input signals shown in the diagrams.

Image of FIG. 2.
FIG. 2.

NAND gate. (a) Demonstration of a spin-wave switch. Left part: output signal without applied current. Right part: output signal with applied current. Suppression of the output pulse is clearly visible. (b) Geometry of a spin-wave NAND gate. The currents and represent the logical inputs ( corresponds to 0, corresponds to 1); the spin-wave interference signal represents the logical output. Inset: truth table for a NAND gate. (c) Gate output signals for input signals as shown in the diagrams.

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/content/aip/journal/apl/92/2/10.1063/1.2834714
2008-01-15
2014-04-17
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752b84549af89a08dbdd7fdb8b9568b5 journal.articlezxybnytfddd
Scitation: Realization of spin-wave logic gates
http://aip.metastore.ingenta.com/content/aip/journal/apl/92/2/10.1063/1.2834714
10.1063/1.2834714
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