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Multilayer atom chips for versatile atom micromanipulation
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10.1063/1.2945893
/content/aip/journal/apl/92/25/10.1063/1.2945893
http://aip.metastore.ingenta.com/content/aip/journal/apl/92/25/10.1063/1.2945893
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Figures

Image of FIG. 1.
FIG. 1.

SEM micrograph of the central part of a multilayer chip. wide wires with a height of cross structures created by e-beam lithography. The smallest features are gaps between wide and high wires. Electrical insulation of the two layers is provided by thick polyimide pads, visible as partially transparent layer.

Image of FIG. 2.
FIG. 2.

Layout of a multilayer atom chip. Left: General view of the chip, size . Contact pads are arranged around the edge of the chip. Wires for trapping of atoms run from top to bottom (blue) on the upmost layer of the chip. Where these wires cross structures on the ground plane, polyimide pads provide insulation of the layers. For longitudinal confinement of the atoms, the chip contains four additional wide wires (dark blue) on the ground plane. Upper right: Central part of the chip , created by e-beam lithography. Lower right: Detail of this central section , similar to the region shown in Fig. 1. Three wide wires (blue) cross submicron structures (light blue, smallest features: wide gaps) separated by polyimide pads.

Image of FIG. 3.
FIG. 3.

(a) Cross section scheme of a multilayer area (not to scale). The step in the upper gold wire causes a bottleneck of reduced cross section. (b) SEM top view of the step. The wire runs from left to right in the upper half of the picture. In the lower right part, the polyimide pad running from top to bottom is visible.

Image of FIG. 4.
FIG. 4.

Left: Temperature evolution of a top layer trapping wire for different applied currents. After , an additional current of is send through two bottom layer confinement wires, as in the experiment shown in Fig. 5. Right: Temperature evolution for different current densities in various chip wires. Solid lines are theoretical predictions according to a simple dissipation model which applies to bottom layer e-beam wires in direct contact with the substrate (Ref. 8). Reduced heat dissipation reduces the current density for top layer wires, currents in the bottom layer wires lead to additional heating (dashed lines to guide the eye).

Image of FIG. 5.
FIG. 5.

(a) Magnetic trapping potential created by the combined fields of the outer bottom layer confinement wires (dark blue), the main top layer trapping wire (blue), and a e-beam fabricated dimple wire (light blue), creating a local potential minimum. (b) In situ absorption images of an atom cloud, evaporatively cooled in the combined potential. Inset: time-of-flight (TOF) absorption image after free expansion, clearly indicating Bose–Einstein condensation.

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/content/aip/journal/apl/92/25/10.1063/1.2945893
2008-06-24
2014-04-20
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752b84549af89a08dbdd7fdb8b9568b5 journal.articlezxybnytfddd
Scitation: Multilayer atom chips for versatile atom micromanipulation
http://aip.metastore.ingenta.com/content/aip/journal/apl/92/25/10.1063/1.2945893
10.1063/1.2945893
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