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(a) Schematic illustration of carbon nanotube network FET with as dielectric. (b) OM image of devices. The channel length is and the channel width is . (c) AFM image of a sparse carbon nanotube network.
(a) curves of a carbon nanotube network FET before (squares) and after (circles) burnout of metallic pathways. (b) Corresponding curves of the FET after electrical breakdown. The gate voltage changes from 0 (bottom) to (top), with steps. (c) vs current on/off ratio.
curves of a device with as dielectric in different sweeping ranges of gate voltages. Inset shows pronounced hystereses in the curves of a similar device with as dielectric.
(a) Inverter, (b) NOR gate logic circuit, and (c) NAND gate logic circuit made from the carbon nanotube network FETs. A loading voltage of and an off-chip resistor of were used in the circuit. Insets show the schematic view of the electronic circuits.
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