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High-performance carbon nanotube network transistors for logic applications
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10.1063/1.2844889
/content/aip/journal/apl/92/6/10.1063/1.2844889
http://aip.metastore.ingenta.com/content/aip/journal/apl/92/6/10.1063/1.2844889
View: Figures

Figures

Image of FIG. 1.
FIG. 1.

(a) Schematic illustration of carbon nanotube network FET with as dielectric. (b) OM image of devices. The channel length is and the channel width is . (c) AFM image of a sparse carbon nanotube network.

Image of FIG. 2.
FIG. 2.

(a) curves of a carbon nanotube network FET before (squares) and after (circles) burnout of metallic pathways. (b) Corresponding curves of the FET after electrical breakdown. The gate voltage changes from 0 (bottom) to (top), with steps. (c) vs current on/off ratio.

Image of FIG. 3.
FIG. 3.

curves of a device with as dielectric in different sweeping ranges of gate voltages. Inset shows pronounced hystereses in the curves of a similar device with as dielectric.

Image of FIG. 4.
FIG. 4.

(a) Inverter, (b) NOR gate logic circuit, and (c) NAND gate logic circuit made from the carbon nanotube network FETs. A loading voltage of and an off-chip resistor of were used in the circuit. Insets show the schematic view of the electronic circuits.

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/content/aip/journal/apl/92/6/10.1063/1.2844889
2008-02-14
2014-04-19
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752b84549af89a08dbdd7fdb8b9568b5 journal.articlezxybnytfddd
Scitation: High-performance carbon nanotube network transistors for logic applications
http://aip.metastore.ingenta.com/content/aip/journal/apl/92/6/10.1063/1.2844889
10.1063/1.2844889
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