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Room temperature Si -growth on Ge incorporating high- dielectric for metal oxide semiconductor applications
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10.1063/1.2957476
/content/aip/journal/apl/93/2/10.1063/1.2957476
http://aip.metastore.ingenta.com/content/aip/journal/apl/93/2/10.1063/1.2957476
View: Figures

Figures

Image of FIG. 1.
FIG. 1.

Core level Si x-ray photoemission spectra of the ML sample, showing the Si–O peak at .

Image of FIG. 2.
FIG. 2.

(a) Cross sectional TEM micrograph of the ML capacitor. (b) The high resolution TEM image shows the high- dielectric layer of thickness and the amorphous interlayer of .

Image of FIG. 3.
FIG. 3.

(a) Multifrequency characteristics measured from the ML capacitor. No kinks for indicate the reduction in interface states near the conduction band edge. The inset captures the gate leakage current density of at . (b) Bidirectional characteristics of ML capacitor at . The inset shows the hysteresis of at the flatband capacitance.

Image of FIG. 4.
FIG. 4.

Interface state analysis in the depletion regime. (a) vs gate bias and (b) vs frequency show frequency and potential dependency of the interface traps. (c) vs surface energy of the interface states , showing to be near the midgap. (d) vs surface energy of the interface states is linear whereby the mean capture cross section of the holes can be estimated to be .

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/content/aip/journal/apl/93/2/10.1063/1.2957476
2008-07-14
2014-04-19
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752b84549af89a08dbdd7fdb8b9568b5 journal.articlezxybnytfddd
Scitation: Room temperature Si δ-growth on Ge incorporating high-K dielectric for metal oxide semiconductor applications
http://aip.metastore.ingenta.com/content/aip/journal/apl/93/2/10.1063/1.2957476
10.1063/1.2957476
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