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The band diagram in high- dielectrics (a) with empty trap state where electrons can be captured; (b) with filled trap state and the gate current is reduced. (c) The schematic of SBD paths in the gate dielectric.
RTN measurement for the device (a) before SRD and (b) after SBD. Capture and emission times are defined in the plot. Note that the gate leakage shows a third-order difference in magnitude.
Calculated capture and emission times as a function gate bias for the devices before and after SBD. Note that emission time, in (b), is field dependent after the SBD.
The dependence of capture time with temperature: (a) pre-SBD; (b) post-SBD. The activation energy shows a huge change for devices after the SBD.
Arrhenius plot for pre- and post-SBD. It shows no changes of with gate bias, at a specific temperature in pre-SBD case. However, it shows gate bias dependent for post-SBD case. This is attributed to a decrease in the cross section as a result of the formation of a SBD induced conductive path.
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