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(a) Schematic of the ZnO/Ag-NP memory TFT and (b) SEM image of the Ag NPs on surface after removing the organics by heating. (c) Cross-sectional HRTEM image of the fabricated device featuring Ag-NPs embedded at the interface.
(a) Output characteristics of ZnO/Ag-NP memory TFT with of 0, 10, …, 40 V and (b) transfer characteristics of the same device demonstrating the clockwise hysteresis for the range of gate bias from to (vice versa) with of 10, 20, …, 50 V and of 3 V. (c) Transfer and hysteresis characteristics of the ZnO-TFTs without Ag-NPs at of 30 V. (d) The hysteresis window vs (circles) and the linear fit (line) result.
(a) Illustration showing the difference in the number of the induced electrons for the same gate bias between the programed and erased state, which is directly related to the shift in . For example, programed memory TFT requires a larger to induce the same number of electrons in channels compared to erased or unprogramed memory TFTs, resulting in the positive shift. (b) Program/erase characteristics of ZnO/Ag-NP memory TFTs, showing the threshold voltage shift on applying pulses with the amplitudes of , , and , respectively, and (c) its charge retention characteristics after applying a pulse of for 1 s.
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