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(a) Schematic illustration of the fabrication process, including cartoons of CMOS inverter logic gates with stretchable, wavy interconnects. Also shown is the strategy of top layer encapsulation to locate the critical circuit elements near the neutral mechanical plane (NMP) to avoid cracking. (b) Image of CMOS inverters with wavy interconnects and bridge structures. (c) Magnified view of a CMOS inverter with wavy interconnects. (d) Three dimensional finite element simulation of the mechanics of this system, showing good agreement with experimental observation; inset shows the location of neutral mechanical plane at the active island region.
(a) Optical images of stretching tests on a silicon CMOS inverter. (b) Profile changes associated with the Poisson effect with applied strain of 3.7% along (left) and (right). (c) Transfer characteristics of stretchable CMOS inverters (red and black: experiment, blue: simulation, left) and variation in inverter threshold voltage for each applied strain in (red) and (black) direction (right); the inset shows log scale transfer curves for individual transistors. (d) Current-voltage curves of an nMOS (left) and pMOS (right) transistor; solid and dotted lines correspond to experiment and simulation, respectively.
(a) Optical images of stretching tests on a silicon CMOS ring oscillator. (b) Oscillation characteristics at different strain values (left: 0s and 0e refer to zero strains at the start and end of the tests, respectively: and refer to tensile strains along and , respectively) and associated frequencies determined by Fourier transformation (right).
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