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The time-dependent melting failure in flip chip lead-free solder interconnects under current stressing
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10.1063/1.2963473
/content/aip/journal/apl/93/4/10.1063/1.2963473
http://aip.metastore.ingenta.com/content/aip/journal/apl/93/4/10.1063/1.2963473
View: Figures

Figures

Image of FIG. 1.
FIG. 1.

(a) A schematic diagram of the stressed test structure and (b) the distribution of current density inside the interconnect stressed by .

Image of FIG. 2.
FIG. 2.

The voltage as a function of time when the interconnect was stressed by at . (The period was denoted as stages I, II, and III with dash-dotted lines.) The inset shows an approximately linear increase in the resistance change ratio with time from (the dotted region).

Image of FIG. 3.
FIG. 3.

SEM images of different stages of the morphological evolution in Sn3.5Ag1.0Cu solder joints under a current density of at after (a) , 25% of the failure time, the time point A, (b) , 66%, B, (c) , 80%, C, (d) , 98%, D, (e) local magnified micrograph of the interface at B, and (f) at C.

Image of FIG. 4.
FIG. 4.

SEM images of the voids in the connecting Al trace (corresponding to the solder interconnect after , the time point D) (a) in the anodic Al trace, and (b) in the cathodic Al trace.

Image of FIG. 5.
FIG. 5.

(a) SEM images of the voids in the connecting Al trace (while voids were unavailable in the Al pad), (b) local magnified micrograph of the voids in the middle Al trace, and (c) in the cathodic Al trace.

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/content/aip/journal/apl/93/4/10.1063/1.2963473
2008-07-30
2014-04-16
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752b84549af89a08dbdd7fdb8b9568b5 journal.articlezxybnytfddd
Scitation: The time-dependent melting failure in flip chip lead-free solder interconnects under current stressing
http://aip.metastore.ingenta.com/content/aip/journal/apl/93/4/10.1063/1.2963473
10.1063/1.2963473
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