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Current percolation in ultrathin channel nanocrystalline silicon transistors
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View: Figures


Image of FIG. 1.
FIG. 1.

(a) The cross-sectional scanning electron microscopy micrograph of the ultrathin channel nanocrystalline silicon (nc-Si) transistors (the minimum channel thickness is ). (b) Top view of the layout design for the nc-Si transistors. (c) Room temperature characteristics for the ultrathin channel nc-Si transistors of thick channel, channel length, and channel width. varies from with a step of .

Image of FIG. 2.
FIG. 2.

(a) characteristics at a drain bias of for thick channel devices of different channel widths, showing the channel width dependence. The displayed current values were normalized for different channel widths, which vary as 0.5, 0.4, 0.3, 0.2, 0.15, 0.1, and in the direction indicated by the arrow. (b) Dependence of on the channel width for different channel thickness devices. was defined as the value of at an of with the drain bias of . We have measured 100 devices for every dimension.

Image of FIG. 3.
FIG. 3.

For the narrow channel, the formation of a current percolation path is limited by the pinch-off at the boundaries, and thus a higher fraction of the conductive grains in the narrow channel is required to achieve current percolation.

Image of FIG. 4.
FIG. 4.

(a) The calculated (the fraction of the conductive grains in the channel) to achieve a normalized conductivity as a function of channel width , showing the narrow channel requires a higher to achieve equally conductive. (b) Illustration to qualitatively describe the relationship between the and the gate voltage with different potential fluctuations over the channel film.


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752b84549af89a08dbdd7fdb8b9568b5 journal.articlezxybnytfddd
Scitation: Current percolation in ultrathin channel nanocrystalline silicon transistors