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Correlation between grain size and device parameters in pentacene thin film transistors
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Image of FIG. 1.

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FIG. 1.

(a) AFM images of pentacene films with the same thickness of 40 nm in four distinct OTFTs A, B, C, and D. Deposition rates of pentacene and substrate surface conditions are shown in the images. (b) Normalized transistor total resistance vs channel length (TLM plots) for OTFT A. Experimental data of (c) and (d) vs gate bias for OTFT A. Straight lines are linear fittings.

Image of FIG. 2.

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FIG. 2.

Normalized channel resistance and contact resistance vs gate bias for (a) OTFTs A and B and for (b) OTFTs C and D. Dependence on pentacene grain size of (c) at , (d) , and (e) at , where data of the three additional devices besides OTFTs A, B, C, and D are added. Grain sizes are estimated from AFM images, and error bars for all the data are shown.

Image of FIG. 3.

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FIG. 3.

Schematics of charge trap sites in a top-contact OTFT. Only one top electrode is shown, and the terracelike morphology of pentacene films is schematically depicted. The meanings of shortenings are described in the text.

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/content/aip/journal/apl/93/4/10.1063/1.2967193
2008-08-01
2014-04-16

Abstract

We develop a general approach to precisely extract the device parameters in top-contact pentacene thin film transistors. The charge trap sites are clarified by analyzing the grain size dependence of the device parameters. The channel mobility and threshold voltage are limited by the charge traps in the channel region, most of which are located not at the grain boundaries but at the organic/insulating-layer interface. The contact resistance decreases by increasing the grain size and is controlled by the charge traps in the contact region, which are suggested to be concentrated at the grain boundaries and at the metal/organic interface.

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Scitation: Correlation between grain size and device parameters in pentacene thin film transistors
http://aip.metastore.ingenta.com/content/aip/journal/apl/93/4/10.1063/1.2967193
10.1063/1.2967193
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