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High-performance nanowire complementary metal-semiconductor inverters
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View: Figures


Image of FIG. 1.
FIG. 1.

Schematic illustration of the major fabrication process for a CMES inverter made on single NW and NW. (a) In/Au Ohmic contact electrodes were defined at the two terminals of one single NW, and a pair of electrodes was patterned by the side of the NW, simultaneously. (b) One NW was assembled between the electrodes pair by the side of the NW via an electric field assembly method. (c) Three Au electrodes were defined. Two of them were patterned at the two terminals of the NW as Ohmic contact electrodes. The other one was the patterned in the middle of the NW as a Schottky gate. (d) An Al electrode was made in the middle of the NW as a Schottky gate. The circuit of the CMES inverter was also plotted in this figure.

Image of FIG. 2.
FIG. 2.

(a) A SEM image of a CMES inverter made with single NW and NW. (b) Two-terminal curves of the . The black and red ones are the curves measured between drain-gate and source-gate, respectively. Inset: magnified drain-gate, source-gate, and source-drain (green line) curves on an exponential scale. [(c) and (d)] and curves for the and NW MESFETs, respectively.

Image of FIG. 3.
FIG. 3.

Performances of the NW CMES inverter depicted in Fig. 2(a). (a) Transfer characteristics of the CMES inverter with , 1 V. Inset: the circuit of the NW CMES inverter. (b) The gains of the inverter. (c) The currents flowing into the inverter. In these figures, the lines in same color are measured simultaneously.


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752b84549af89a08dbdd7fdb8b9568b5 journal.articlezxybnytfddd
Scitation: High-performance nanowire complementary metal-semiconductor inverters