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Cross-sectional TEM micrograph of a 49 nm thick film deposited on (100) Si. The inset shows a close-up of the interlayer, which has a thickness of about 2.5 nm.
XRD patterns of a thick, as deposited film grown on (100) Si, together with those after annealing at different temperatures in 1 atm gas for 20 s.
Capacitance normalized to the gate area vs gate voltage of MOS capacitors with different oxide thicknesses.
Calculated CET vs of MOS capacitors. The slope of the best-fit line indicates that and its intercept at 2.5 nm on the CET axis corresponds to the electrical thickness of the lower- interfacial layer.
vs CET. The intercept of the best-fit line on the axis gives and the slope .
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