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thin films as an alternative gate dielectric
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10.1063/1.2968660
/content/aip/journal/apl/93/5/10.1063/1.2968660
http://aip.metastore.ingenta.com/content/aip/journal/apl/93/5/10.1063/1.2968660
View: Figures

Figures

Image of FIG. 1.
FIG. 1.

Cross-sectional TEM micrograph of a 49 nm thick film deposited on (100) Si. The inset shows a close-up of the interlayer, which has a thickness of about 2.5 nm.

Image of FIG. 2.
FIG. 2.

XRD patterns of a thick, as deposited film grown on (100) Si, together with those after annealing at different temperatures in 1 atm gas for 20 s.

Image of FIG. 3.
FIG. 3.

Capacitance normalized to the gate area vs gate voltage of MOS capacitors with different oxide thicknesses.

Image of FIG. 4.
FIG. 4.

Calculated CET vs of MOS capacitors. The slope of the best-fit line indicates that and its intercept at 2.5 nm on the CET axis corresponds to the electrical thickness of the lower- interfacial layer.

Image of FIG. 5.
FIG. 5.

vs CET. The intercept of the best-fit line on the axis gives and the slope .

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/content/aip/journal/apl/93/5/10.1063/1.2968660
2008-08-05
2014-04-17
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752b84549af89a08dbdd7fdb8b9568b5 journal.articlezxybnytfddd
Scitation: SmScO3 thin films as an alternative gate dielectric
http://aip.metastore.ingenta.com/content/aip/journal/apl/93/5/10.1063/1.2968660
10.1063/1.2968660
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