Full text loading...
A schematic illustration of NCs fabrication on the sidewall and top of the vertical floating gate memory. (a) PS-PVP micellar solution. (b) PS-PVP micellar solution with in the PVP core. (c) Monolayer of PS-PVP micelles coated on the sidewall and top. (d) Array of NCs on the sidewall and top surface.
A SEM image of Co NCs on (a) the top surface and (b) the sidewall surface. The inset shows a 3D schematic diagram of the 3D vertical floating gate memory with NCs on the sidewall and the top.
(a) The memory characteristics of the fabricated vertical floating gate memory device with pulses of for 100 ms for the program/erase operations. (b) The effect of hydrogen annealing on memory performance. The programing pulse was 11 V for 100 ms.
The measured data retention characteristics of the vertical floating gate memory devices (a) with and (b) without hydrogen annealing at room temperature after the application of a pulse of 13 V for 1 ms.
Article metrics loading...