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Surface property controllable multilayered gate dielectric for low voltage organic thin film transistors
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10.1063/1.2973160
/content/aip/journal/apl/93/8/10.1063/1.2973160
http://aip.metastore.ingenta.com/content/aip/journal/apl/93/8/10.1063/1.2973160
View: Figures

Figures

Image of FIG. 1.
FIG. 1.

(a) FTIR transmission spectra of the PDMS layer at various UVO treatment times. (b) Surface energy and contact angle of water as a function of UVO treatment time for the PDMS layer. Gate dielectrics , , , and after UVO treatment times of 0, 5, 15, and 30 min, respectively.

Image of FIG. 2.
FIG. 2.

Tapping mode AFM topographic images of 50 nm thick pentacene films deposited on a layer at various UVO treatment times: (a) UVO 0 min, (b) UVO 5 min, (c) UVO 15 min, and (d) UVO 30 min. Inset shows water droplet images on a layer.

Image of FIG. 3.
FIG. 3.

Transfer characteristics of pentacene TFTs fabricated on a layer at various UVO treatment times: (a) and (b) .

Image of FIG. 4.
FIG. 4.

AFM images of pentacene films deposited on a layer with nominal thicknesses of 1, 3, 5, and 10 nm, respectively. UVO treatments for (a) 5 min and (b) 15 min.

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/content/aip/journal/apl/93/8/10.1063/1.2973160
2008-08-26
2014-04-16
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752b84549af89a08dbdd7fdb8b9568b5 journal.articlezxybnytfddd
Scitation: Surface property controllable multilayered gate dielectric for low voltage organic thin film transistors
http://aip.metastore.ingenta.com/content/aip/journal/apl/93/8/10.1063/1.2973160
10.1063/1.2973160
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