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Strain effect and channel length dependence of bias temperature instability on complementary metal-oxide-semiconductor field effect transistors with high- gate stacks
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10.1063/1.2967442
/content/aip/journal/apl/93/9/10.1063/1.2967442
http://aip.metastore.ingenta.com/content/aip/journal/apl/93/9/10.1063/1.2967442
View: Figures

Figures

Image of FIG. 1.
FIG. 1.

Both simulated (dash lines) and measured (solid circle and square) threshold voltage shifts of the 65 nm dual metal gate CMOSFET with and without a tensile strain under NBTI and PBTI stresses as a function of channel length.

Image of FIG. 2.
FIG. 2.

losses of pMOSFET under NBTI stress and nMOSFET under PBTI stress with and without a tensile strain as a function of channel length.

Image of FIG. 3.
FIG. 3.

The threshold voltage shifts of the HfSiON/ dual metal gate CMOSFET with different channel lengths (square for , circle for , and triangle for 60 nm) under NBTI (left) and PBTI (right) stresses as a function of electric stress field. The inset represents the of HfSiON/ gate stack as a function of channel length. Two stress voltages ( and ) are adopted to extrapolate the relation between electric stress field and threshold voltage shifts.

Image of FIG. 4.
FIG. 4.

The ratio of substrate current density to gate current density as a function of channel length under constant electric field for pMOSFET. The inset is the schematic band diagram of high- nMOSFETs with thick (dash) and thin (solid) ILs under constant field NBTI stress, respectively.

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/content/aip/journal/apl/93/9/10.1063/1.2967442
2008-09-02
2014-04-23
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752b84549af89a08dbdd7fdb8b9568b5 journal.articlezxybnytfddd
Scitation: Strain effect and channel length dependence of bias temperature instability on complementary metal-oxide-semiconductor field effect transistors with high-k/SiO2 gate stacks
http://aip.metastore.ingenta.com/content/aip/journal/apl/93/9/10.1063/1.2967442
10.1063/1.2967442
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