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Both simulated (dash lines) and measured (solid circle and square) threshold voltage shifts of the 65 nm dual metal gate CMOSFET with and without a tensile strain under NBTI and PBTI stresses as a function of channel length.
losses of pMOSFET under NBTI stress and nMOSFET under PBTI stress with and without a tensile strain as a function of channel length.
The threshold voltage shifts of the HfSiON/ dual metal gate CMOSFET with different channel lengths (square for , circle for , and triangle for 60 nm) under NBTI (left) and PBTI (right) stresses as a function of electric stress field. The inset represents the of HfSiON/ gate stack as a function of channel length. Two stress voltages ( and ) are adopted to extrapolate the relation between electric stress field and threshold voltage shifts.
The ratio of substrate current density to gate current density as a function of channel length under constant electric field for pMOSFET. The inset is the schematic band diagram of high- nMOSFETs with thick (dash) and thin (solid) ILs under constant field NBTI stress, respectively.
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