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Electrons and holes in a 40 nm thick silicon slab at cryogenic temperatures
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View: Figures


Image of FIG. 1.
FIG. 1.

(a) Schematic diagram of a cross-section through the device. (b) Optical image of the Hall-bar device with a circuit diagram illustrating the setup for two-terminal measurements.

Image of FIG. 2.
FIG. 2.

(a) Current through - (: solid lines) and -contacts (: dashed lines) at different taken with a bias of 10 mV. [(b) and (c)] Schematics of the potential required for coexistence without (b) and with (c) quantum confinement. (d) As (c) but with potential symmetrically reversed. (e) As (d) but with a bias applied to the 2D hole gas.

Image of FIG. 3.
FIG. 3.

(a) Diagonal resistivity of the -channel as functions of magnetic field and interlayer bias applied through a -contact with gate voltages fixed at and . (b) Schematic diagram illustrating the setup used in (a). (c) Schematic diagram illustrating regions of the plane with an interlayer bias of 0.6 V. Solid lines demarcate lines of zero electron (blue) and hole (red) density, while dashed lines indicate zero density of a second subband of a given carrier-type. The central diamond-shaped region bound by four solid lines corresponds to a situation where there are no carriers in the silicon slab. [(d) and (e)] Diagonal conductivity measured with -channel contacts and -channel contacts , respectively, at , with an interlayer bias of 0.6 V. Identical points are marked by circles in (a) and (d).

Image of FIG. 4.
FIG. 4.

[(a) and (b)] and , respectively, with no interlayer bias. [(c) and (d)] and , respectively, with an interlayer bias of 0.6 V. Solid lines represent expected lines of zero carrier density for the carrier-type being measured while dashed lines correspond to the other carrier-type.

Image of FIG. 5.
FIG. 5.

Electron-hole drag at , . (a) . [(b) and (c)] . and agree well for marked by the vertical dotted line. Inset: Setting for measuring .


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752b84549af89a08dbdd7fdb8b9568b5 journal.articlezxybnytfddd
Scitation: Electrons and holes in a 40 nm thick silicon slab at cryogenic temperatures