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Gate-controlled nonvolatile graphene-ferroelectric memory
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10.1063/1.3119215
/content/aip/journal/apl/94/16/10.1063/1.3119215
http://aip.metastore.ingenta.com/content/aip/journal/apl/94/16/10.1063/1.3119215
View: Figures

Figures

Image of FIG. 1.
FIG. 1.

(a) Sample geometry of a finished graphene-ferroelectric memory device. (b) Optical image of a graphene sample showing the Hall bar geometry of the bottom electrodes. (c) vs of the graphene sample before P(VDF-TrFE) coating, measured in two-terminal configuration. (d) AFM image of another graphene sample after P(VDF-TrFE) spin coating. The contrast comes from the slightly different crystallization of P(VDF-TrFE) on , graphene, and Au electrodes, respectively. (e) Optical image of a finished device.

Image of FIG. 2.
FIG. 2.

Electric hysteresis loop. as a function of for the graphene-ferroelectric sample. The resistance peak at 44 V (−32 V) corresponds to the flipping of electric dipoles in P(VDF-TrFE) from upward (downward) to downward (upward). From the linear part of this curve at high voltage, the charge carrier mobility is estimated to be , taking (Ref. 23).

Image of FIG. 3.
FIG. 3.

vs characteristics deduced from the vs curve in Fig. 2. The black curve represents the experimental measured of P(VDF-TrFE) thin film with similar thickness. The kinks near in are caused by the assumption of a constant charge carrier mobility, which does not hold near the charge neutral regime. Inset (a): the electric displacement continuity equation at ferroelectric/graphene interface. Inset (b): a polarized P(VDF-TrFE) molecule. Cyan, gray, and white atoms represent fluorine, carbon, and hydrogen, respectively.

Image of FIG. 4.
FIG. 4.

(a) Writing 0 into graphene-ferroelectric memory by a full loop sweep of (±85 V). The memory bit is in the 0 state before writing. (b) Writing 1 into graphene-ferroelectric memory by an asymmetrical loop sweep of (from 85 to −34 V). The memory bit is in the 1 state before writing. (c) Writing 0 into graphene-ferroelectric memory by a full loop sweep of . The memory bit is in the 1 state before writing. (d) Writing 1 into graphene-ferroelectric memory by an asymmetrical loop sweep of . The memory bit is in the 0 state before writing.

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/content/aip/journal/apl/94/16/10.1063/1.3119215
2009-04-22
2014-04-25
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752b84549af89a08dbdd7fdb8b9568b5 journal.articlezxybnytfddd
Scitation: Gate-controlled nonvolatile graphene-ferroelectric memory
http://aip.metastore.ingenta.com/content/aip/journal/apl/94/16/10.1063/1.3119215
10.1063/1.3119215
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