Full text loading...
TEM cross sectional images for six FD-SOI structures with varying from 15.5 to 72.3 nm.
(a) Top silicon thickness vs transverse electric field at −20 V of back substrate bias. The magnitude of transverse electric field was 210 and 35 kV/cm at 16 and 72 nm, respectively. (b) Top silicon thickness vs threshold voltage at −20 V of back substrate bias. Threshold voltage decreases at 143 mV with increasing top silicon thickness from 16 to 72 nm.
characteristics of FD-SOI Cap-less memory cell showing top silicon thickness dependency when back substrate bias voltage of −20 V is applied.
Lateral electric field and conduction current density for each . Impact ionization rate is maximized at specific top silicon thickness, 45 nm, by above factors.
(a) Drain current measured at (, the opened) and (, the closed). Circle symbol shows experimental results and square symbol shows simulation results. (b) Memory margins of each sample measured by difference between and currents. The maximum memory margin is at top silicon thickness of 46.9 nm. It was shown that memory margin at 46.9 nm is 3.38 times larger than that at 15.5 nm.
Article metrics loading...