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Gate-defined quantum-dot devices realized in InGaAs/InP by incorporating a layer as gate dielectric
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10.1063/1.3077188
/content/aip/journal/apl/94/4/10.1063/1.3077188
http://aip.metastore.ingenta.com/content/aip/journal/apl/94/4/10.1063/1.3077188
View: Figures

Figures

Image of FIG. 1.
FIG. 1.

Linear-response conductance of a gate-defined QPC in an InGaAs/InP heterostructure measured against the split-gate voltage at 4.2 K. The inset shows an AFM image of the QPC device and a schematic diagram of the measurement circuit.

Image of FIG. 2.
FIG. 2.

Source-drain current vs plunger gate voltage measured for a QD in InGaAs/InP defined by setting other gate voltages at values of , , and . The inset shows the scanning electron microscope image of the QD device and a schematic diagram of the measurement setup. The device is measured at 300 mK with .

Image of FIG. 3.
FIG. 3.

(a) Charge stability diagram and (b) magnetic-field evolution of the Coulomb blockade peaks of a gate-defined QD device (see text for details). In (a) the differential conductance is plotted as a function of and and in (b) the linear-response conductance is plotted as a function of and the perpendicular magnetic field .

Image of FIG. 4.
FIG. 4.

(a) Charge stability diagram and (b) magnetic-field evolution of the Coulomb blockade peaks of a gate-defined QD device (see text for details). In (a) the differential conductance is plotted as a function of and and in (b) the linear-response conductance is plotted as a function of and the parallel magnetic field .

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/content/aip/journal/apl/94/4/10.1063/1.3077188
2009-01-30
2014-04-19
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752b84549af89a08dbdd7fdb8b9568b5 journal.articlezxybnytfddd
Scitation: Gate-defined quantum-dot devices realized in InGaAs/InP by incorporating a HfO2 layer as gate dielectric
http://aip.metastore.ingenta.com/content/aip/journal/apl/94/4/10.1063/1.3077188
10.1063/1.3077188
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