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Realization of dual-gated core-shell nanowire field effect transistors with highly doped source and drain
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10.1063/1.3079410
/content/aip/journal/apl/94/6/10.1063/1.3079410
http://aip.metastore.ingenta.com/content/aip/journal/apl/94/6/10.1063/1.3079410
View: Figures

Figures

Image of FIG. 1.
FIG. 1.

(a) Schematic representation of a core-shell NW dispersed on a substrate. (b) ALD of on the NW. (c) Gate metal (TaN) deposition and layer etching, followed by B ion implantation (d) B activation anneal and Ni deposition on the S/D regions. (e) SEM of a NW dual-gated FET device with Ni contacts. The red regions G represent the gates, and the yellow regions represent the S/D.

Image of FIG. 2.
FIG. 2.

Electrical characteristics of a core-shell NW FET with undoped S/D, and with a channel length . (a) vs data measured at different values. (b) vs data measured at different values. The data in both panels were measured at two back-gate biases: (square, black symbols) and (round, red symbols).

Image of FIG. 3.
FIG. 3.

(a) vs data measured at different values for a core-shell NW FET with doped S/D. Inset: vs measured at different values for the same device. (b) The vs data of Fig. 2 measured at for a core-shell NW FET with undoped S/D are shown for comparison. Inset: vs data of the same device. The devices of panels (a) and (b) have similar channel lengths, .

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/content/aip/journal/apl/94/6/10.1063/1.3079410
2009-02-12
2014-04-25
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752b84549af89a08dbdd7fdb8b9568b5 journal.articlezxybnytfddd
Scitation: Realization of dual-gated Ge–SixGe1−x core-shell nanowire field effect transistors with highly doped source and drain
http://aip.metastore.ingenta.com/content/aip/journal/apl/94/6/10.1063/1.3079410
10.1063/1.3079410
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