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1.
1.The International Technology Roadmap for Semiconductors 2008 Update.
2.
2.P. Avouris, Z. Chen, and V. Perebeinos, Nat. Nanotechnol. 2, 605 (2007).
http://dx.doi.org/10.1038/nnano.2007.300
3.
3.A. K. Geim and K. S. Novoselov, Nature Mater. 6, 183 (2007).
http://dx.doi.org/10.1038/nmat1849
4.
4.P. Avouris, J. Appenzeller, R. Martel, and S. J. Wind, Proc. IEEE 91, 1772 (2003).
http://dx.doi.org/10.1109/JPROC.2003.818338
5.
5.S. J. Kang, C. Kocabas, T. Ozel, M. Shim, N. Pimparkar, M. A. Alam, S. V. Rotkin, and J. A. Rogers, Nat. Nanotechnol. 2, 230 (2007).
http://dx.doi.org/10.1038/nnano.2007.77
6.
6.S. Y. Zhou, G. -H. Gweon, A. V. Fedorov, P. N. First, W. A. de Heer, D. -H. Lee, F. Guinea, A. H. C. Neto, and A. Lanzara, Nature Mater. 6, 770 (2007).
http://dx.doi.org/10.1038/nmat2003
7.
7.A. Reina, X. Jia, J. Ho, D. Nezich, H. Son, V. Bulovic, M. S. Dresselhaus, and J. Kong, Nano Lett.9, 30 (2009).
http://dx.doi.org/10.1021/nl801827v
8.
8.X. Liang, Z. Fu, and S. Y. Chou, Nano Lett. 7, 3840 (2007).
http://dx.doi.org/10.1021/nl072566s
9.
9.V. C. Tung, M. J. Allen, Y. Yang, and R. B. Kaner, Nat. Nanotechnol. 4, 25 (2009).
http://dx.doi.org/10.1038/nnano.2008.329
10.
10.M. Y. Han, B. Özyilmaz, Y. Zhang, and P. Kim, Phys. Rev. Lett. 98, 206805 (2007).
http://dx.doi.org/10.1103/PhysRevLett.98.206805
11.
11.K. I. Bolotin, K. J. Sikes, Z. Jiang, M. Klima, G. Fudenberg, J. Hone, P. Kim, and H. L. Stormer, Solid State Commun. 146, 351 (2008).
http://dx.doi.org/10.1016/j.ssc.2008.02.024
12.
12.X. Du, I. Skachko, A. Barker, and E. Y. Andrei, Nat. Nanotechnol. 3, 491 (2008).
http://dx.doi.org/10.1038/nnano.2008.199
13.
13.J. D. Meindl, Q. Chen, and J. A. Davis, Science 293, 2044 (2001).
http://dx.doi.org/10.1126/science.293.5537.2044
14.
14.K. S. Novoselov, A. K. Geim, S. V. Morozov, D. Jiang, Y. Zhang, S. V. Dubonos, I. V. Grigorieva, and A. A. Firsov, Science 306, 666 (2004).
http://dx.doi.org/10.1126/science.1102896
15.
15.M. C. Lemme, T. J. Echtermeyer, M. Baus, and H. Kurz, IEEE Electron Device Lett. 28, 282 (2007).
http://dx.doi.org/10.1109/LED.2007.891668
16.
16.T. Ohta, A. Bostwick, T. Seyller, K. Horn, and E. Rotenberg, Science 313, 951 (2006).
http://dx.doi.org/10.1126/science.1130681
17.
17.X. Li, X. Wang, L. Zhang, S. Lee, and H. Dai, Science 319, 1229 (2008).
http://dx.doi.org/10.1126/science.1150878
18.
18.T. J. Echtermeyer, M. C. Lemme, M. Baus, B. N. Szafranek, A. K. Geim, and H. Kurz, IEEE Electron Device Lett. 29, 952 (2008).
http://dx.doi.org/10.1109/LED.2008.2001179
19.
19.N. Yokoyama, K. Imamura, S. Muto, S. Hiyamizu, and H. Nishi, Jpn. J. Appl. Phys., Part 2 24, L853 (1985).
http://dx.doi.org/10.1143/JJAP.24.L853
20.
20.Y. Takahashi, A. Fujiwara, K. Yamazaki, H. Namatsu, K. Kurihara, and K. Murase, Appl. Phys. Lett. 76, 637 (2000).
http://dx.doi.org/10.1063/1.125843
21.
21.M. Saitoh and T. Hiramoto, Electron. Lett. 40, 836 (2004).
http://dx.doi.org/10.1049/el:20040554
22.
22.T. Kitade, K. Ohkura, and A. Nakajima, Appl. Phys. Lett. 86, 123118 (2005).
http://dx.doi.org/10.1063/1.1894594
23.
23.S. -M. Kang and Y. Leblebici, CMOS Digital Integrated Circuits Analysis Design (McGraw-Hill, New York, 2002).
24.
24.J. -M. Wang, S. -C. Fang, and W. -S. Feng, IEEE J. Solid-State Circuits 29, 780 (1994).
http://dx.doi.org/10.1109/4.303715
25.
25.A. C. Ferrari, J. C. Meyer, V. Scardaci, C. Casiraghi, M. Lazzeri, F. Mauri, S. Piscanec, D. Jiang, K. S. Novoselov, S. Roth, and A. K. Geim, Phys. Rev. Lett. 97, 187401 (2006).
http://dx.doi.org/10.1103/PhysRevLett.97.187401
26.
26.L. Liu, S. Ryu, M. R. Tomasik, E. Stolyarova, N. Jung, M. S. Hybertsen, M. L. Steigerwald, L. E. Brus, and G. W. Flynn, Nano Lett. 8, 1965 (2008).
http://dx.doi.org/10.1021/nl0808684
27.
27.J. Martin, N. Akerman, G. Ulbricht, T. Lohmann, J. H. Smet, K. V. Klitzing, and A. Yacoby, Nat. Phys. 4, 144 (2008).
http://dx.doi.org/10.1038/nphys781
28.
28.P. Avouris, Acc. Chem. Res. 35, 1026 (2002).
http://dx.doi.org/10.1021/ar010152e
29.
29.S. M. Sze, Physics of Semiconductor Devices (Wiley-Interscience, New York, 1981).
30.
30.X. Wang, Y. Ouyang, X. Li, H. Wang, J. Guo, and H. Dai, Phys. Rev. Lett. 100, 206803 (2008).
http://dx.doi.org/10.1103/PhysRevLett.100.206803
31.
31.R. Sordan, K. Balasubramanian, M. Burghard, and K. Kern, Appl. Phys. Lett. 88, 053119 (2006).
http://dx.doi.org/10.1063/1.2171474
32.
32.R. Sordan, A. Miranda, J. Osmond, D. Chrastina, G. Isella, and H. von Känel, Appl. Phys. Lett. 89, 152122 (2006).
http://dx.doi.org/10.1063/1.2362989
33.
33.K. Mistry, C. Allen, C. Auth, B. Beattie, D. Bergstrom, M. Bost, M. Brazier, M. Buehler, A. Cappellani, R. Chau et al., Tech. Dig. - Int. Electron Devices Meet. 2007, 247.
http://dx.doi.org/10.1109/IEDM.2007.4418914
34.
34.Y. -M. Lin, K. A. Jenkins, A. Valdes-Garcia, J. P. Small, D. B. Farmer, and P. Avouris, Nano Lett. 9, 422 (2009).
http://dx.doi.org/10.1021/nl803316h
35.
35.J. Moser, A. Barreiro, and A. Bachtold, Appl. Phys. Lett. 91, 163513 (2007).
http://dx.doi.org/10.1063/1.2789673
36.
36.B. Özyilmaz, P. Jarillo-Herrero, D. Efetov, and P. Kim, Appl. Phys. Lett. 91, 192107 (2007).
http://dx.doi.org/10.1063/1.2803074
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/content/aip/journal/apl/94/7/10.1063/1.3079663
2009-02-18
2015-05-03

Abstract

The operation of four basic two-input logic gates fabricated with a single graphenetransistor is demonstrated. Single-transistor operation is obtained in a circuit designed to exploit the charge neutrality point of graphene to perform Boolean logic. The type of logic function is selected by offset of the input digital signals. The merits and limitations of the fabricated gates are assessed by comparing their performance with that of conventional logic gates.

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Scitation: Logic gates with a single graphene transistor
http://aip.metastore.ingenta.com/content/aip/journal/apl/94/7/10.1063/1.3079663
10.1063/1.3079663
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