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Schematic diagrams for the architecture of present device cell consisting of the counter electrode (CE) opposite to the source (s) and drain (d).
Current density versus bias voltage for the present device in the dark (off state) and under illumination (on state). The inset is the calculated differential conductance.
Characteristic transport loops for (left axis) and (right axis) for the present device. The inset is a schematic diagram showing the effective dyed- area of on source and on drain, respectively.
Photoexcited voltage versus bias voltage for the characterization of the difference between and : (a) versus examined during the loop measurement. The rectangle frame notes the part corresponding to . (b) Enlarged rectangle frame of (a) as (left axis) and the partial plot of Fig. 3 as (right axis).
Schematic diagram for the various potential levels involving the present device cells. The solid lines represent the dominant direction of electron flowing, and the dash lines represent the potential direction of electron movement.
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