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Size-dependent modulation of carrier mobility in top-down fabricated silicon nanowires
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View: Figures


Image of FIG. 1.
FIG. 1.

(a) Electron and hole mobility vs inversion carrier density in Si NW FETs with a rectangular cross section. The height of the NWs is and the width is in the 7–23 nm range. Inset: NW cross section with (100) top/bottom surfaces and (110) sidewalls. (b) Width dependence of in Si NW FETs at inversion carrier density normalized by the mobility of the widest NWs (20 nm for NFETs and 23 nm for PFETs). The solid lines are normalized electron and hole mobilities expected in Si NWs assuming a simple facet-dominated transport model.

Image of FIG. 2.
FIG. 2.

(a) NW facet orientations used for stress simulations. The longitudinal/transverse/vertical (L/T/V) directions are relative to current flow for the top/bottom surfaces and the sidewalls. (b) Calculated profiles of electron density and stress, , , and , across the cross section of Si NWs with height , and width and 22 nm. The stress profiles are normalized by the gate oxide stress .

Image of FIG. 3.
FIG. 3.

(a) Fraction of electron charge at (100) top/bottom surfaces, (110) sidewalls, and corners, and in bulk vs NW width . Inset: Schematic of one-quarter of the NW showing the assignment of the four components of charge. (b) Calculated average of the three components of stress , , and vs assuming gate oxide stress . (c) Width dependence of electron and hole mobility under stress, calculated assuming bulk and 2D inversion layer piezoresistive coefficients . is normalized by its value at .


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752b84549af89a08dbdd7fdb8b9568b5 journal.articlezxybnytfddd
Scitation: Size-dependent modulation of carrier mobility in top-down fabricated silicon nanowires