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Patterned electrode vertical field effect transistor fabricated using block copolymer nanotemplates
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Image of FIG. 1.

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FIG. 1.

(a) Schematic illustration and (b) side view, of a grid-patterned source-electrode vertical FET.

Image of FIG. 2.

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FIG. 2.

Calculated charge density distribution inside the active-layer for two gate bias conditions and injection barriers at the source of 0.7 eV and . (a) For . (b) For . (c) For .

Image of FIG. 3.

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FIG. 3.

AFM surface analysis. Top image, microphase separated PS-PMMA structure, featuring protruding PS cylinders from a PMMA matrix. Middle image, PS pattern over left after PMMA removal; depth analysis indicates cylinders in the height of 40–50 nm. Bottom image, the patterned metal grid; depth analysis confirms the metal layer deposition thickness and complete lift-off, in this case around 10 nm.

Image of FIG. 4.

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FIG. 4.

Transfer characteristics of the patterned source electrode VOFET. The device shows On/Off ratio of .

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/content/aip/journal/apl/95/21/10.1063/1.3266855
2009-11-23
2014-04-24

Abstract

We report the design and implementation of a vertical organic field effect transistor which is compatible with standard devicefabrication technology and is well described by a self consistent device model. The active semiconductor is a film of molecules, and the device operation is based on the architecture of the nanopatterned source electrode. The relatively high resolution fabrication process and maintaining the low-cost and simplicity associated with organic electronics, necessitates unconventional fabrication techniques such as soft lithography. Block copolymer self-assembled nanotemplates enable the production of conductive, gridlike metal electrode. The devices reported here exhibit On/Off ratio of .

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Scitation: Patterned electrode vertical field effect transistor fabricated using block copolymer nanotemplates
http://aip.metastore.ingenta.com/content/aip/journal/apl/95/21/10.1063/1.3266855
10.1063/1.3266855
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