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Compact silicon double and triple dots realized with only two gates
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View: Figures


Image of FIG. 1.
FIG. 1.

Schematic layout of the coupled MOS-SETs: (a) long silicon nitride spacers protecting the central region of SOI during source-drain implantation (samples 1 and 2). (b) with short spacers a dot is created by implanted arsenic donors in the central region (sample 3). Below each case the schematic profiles of the bottom of the conduction band are drawn for various gate voltages. The horizontal line is the Fermi energy fixed by the source and drain. (c) SEM micrograph of a typical sample before spacers deposition. The gate length is 60 nm and the spacing between gate 30 nm. (d) Equivalent circuit for the triple dot system. The capacitance values corresponding to sample 2 are given in aF.

Image of FIG. 2.
FIG. 2.

Source-drain conductance at vs gate voltages for sample 1: , , , and 40 nm spacers. From left (two capacitively coupled MOS-SETs) to right (single dot) gate-controlled interdot coupling increases.

Image of FIG. 3.
FIG. 3.

Source-drain conductance vs gate voltages at . (a) sample 2: , , , and 40 nm spacers. (b) Sample 3: , , , and 15 nm spacers. Periodic antidiagonals occur at each degeneracy point of a central dot formed between the two gates. The period is 2.5 larger for sample 2 (large spacers) compared to sample 3 (small spacers), indicating that the central dot is bigger due to local doping. In that case the source-drain current appears at lower gate voltages.

Image of FIG. 4.
FIG. 4.

(a) Source-drain conductance vs gate voltages for sample 2 at near degeneracy of the central dot. Hexagonal cells are distorted into pentagonal and diamond-shaped features. (b) simulation at of the triple dot sketched in Fig. 1(d). are indicated with an arbitrary origin [(0,0,0) corresponds to about (60,20,60)] because the figure is periodic in , , and .


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752b84549af89a08dbdd7fdb8b9568b5 journal.articlezxybnytfddd
Scitation: Compact silicon double and triple dots realized with only two gates