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An illustration of cross-section view of CGLC n-TFT, hot carrier effect on CGLC n-TFT, and shift in threshold voltage on CGLC n-TFT under dc voltage stress.
The difference of before and after stressed curve (initial capacitance curve minus stressed capacitance curve) clearly represented the feature trend. The abbreviated graph presented the gate-to-drain capacitance vs gate voltage. curve.
The capacitor model as (a) gate voltage is less than −3 V , (b) gate voltage is between −3 and 1.25 V , and (c) gate voltage is greater than 1.25 V . (d) The simulation of vertical and lateral electrical field from TCAD tool.
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