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Gate-to-drain capacitance verifying the continuous-wave green laser crystallization n-TFT trapped charges distribution under dc voltage stress
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10.1063/1.3275728
/content/aip/journal/apl/95/25/10.1063/1.3275728
http://aip.metastore.ingenta.com/content/aip/journal/apl/95/25/10.1063/1.3275728
View: Figures

Figures

Image of FIG. 1.
FIG. 1.

An illustration of cross-section view of CGLC n-TFT, hot carrier effect on CGLC n-TFT, and shift in threshold voltage on CGLC n-TFT under dc voltage stress.

Image of FIG. 2.
FIG. 2.

The difference of before and after stressed curve (initial capacitance curve minus stressed capacitance curve) clearly represented the feature trend. The abbreviated graph presented the gate-to-drain capacitance vs gate voltage. curve.

Image of FIG. 3.
FIG. 3.

The capacitor model as (a) gate voltage is less than −3 V , (b) gate voltage is between −3 and 1.25 V , and (c) gate voltage is greater than 1.25 V . (d) The simulation of vertical and lateral electrical field from TCAD tool.

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/content/aip/journal/apl/95/25/10.1063/1.3275728
2009-12-23
2014-04-16
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752b84549af89a08dbdd7fdb8b9568b5 journal.articlezxybnytfddd
Scitation: Gate-to-drain capacitance verifying the continuous-wave green laser crystallization n-TFT trapped charges distribution under dc voltage stress
http://aip.metastore.ingenta.com/content/aip/journal/apl/95/25/10.1063/1.3275728
10.1063/1.3275728
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