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Scanning electron micrograph of the mirror pair device (b), with the measurement set-up for the AlTiAl device drawn. Inset: a schematic of the gap profiles for the AlTiAl SSET (left) and TiAlTi SSET (right).
(a) Stability diagram of on the plane of bias and normalized gate voltage . To emphasize the observed current features we plot ; the white (dark) areas correspond to higher (lower) current with a range of . We modeled the voltage conditions for Cooper pair tunneling (solid line), QP tunneling (dotted line) and tunneling (dashed line). (b) Stability diagram of with given in arbitrary units, again lighter areas correspond to higher current. (c) Cross section of (a) at constant bias voltage, . (d) Cross section of (b) at constant bias voltage, .
(a) Gate modulations in vs gate voltage for with increasing temperature. Curves are vertically offset by 0.5 nA for clarity. Each temperature measurement was performed separately; therefore curves were horizontally aligned to account for charge jumps. (b) Amplitude of the gate modulation in vs temperature for a TiAlTi SSET fabricated to extract the of Ti.
Sample parameters of AlTiAl and TiAlTi SSETs. Here the sum of the Al and Ti gaps is given by , is the normal-state resistance of the two junctions in series, is the charging energy, is the Josephson energy, corresponds to the deposition, Ox gives the oxidation pressure and time, and is the observed periodicity of the gate modulations.
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