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Characteristics of an electroless plated-gate transistor
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10.1063/1.3202404
/content/aip/journal/apl/95/5/10.1063/1.3202404
http://aip.metastore.ingenta.com/content/aip/journal/apl/95/5/10.1063/1.3202404
View: Figures

Figures

Image of FIG. 1.
FIG. 1.

The AES depth profile analysis of the studied EP-device. The insets show the simplified device structure, EP reaction on the AlGaAs layer surface, and SEM picture of the cross section of the studied device.

Image of FIG. 2.
FIG. 2.

The forward voltage and gate leakage current as a function of inverse temperature . The inset shows the logarithmic value of versus gate-drain voltage of the EP-device at various temperatures.

Image of FIG. 3.
FIG. 3.

The maximum transconductance , drain saturation current , and operating regime as a function of inverse temperature . The biased voltage is fixed at . The inset shows normalized and on the stress time, under stress conditions of at 420, 450, and 480 K.

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/content/aip/journal/apl/95/5/10.1063/1.3202404
2009-08-06
2014-04-23
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752b84549af89a08dbdd7fdb8b9568b5 journal.articlezxybnytfddd
Scitation: Characteristics of an electroless plated-gate transistor
http://aip.metastore.ingenta.com/content/aip/journal/apl/95/5/10.1063/1.3202404
10.1063/1.3202404
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