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Gate-bias stress in amorphous oxide semiconductors thin-film transistors
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10.1063/1.3187532
/content/aip/journal/apl/95/6/10.1063/1.3187532
http://aip.metastore.ingenta.com/content/aip/journal/apl/95/6/10.1063/1.3187532

Figures

Image of FIG. 1.
FIG. 1.

as function of time on a logarithmic scale. The continuous curve is a fit with stretched-exponential time dependence. The inset shows the drain current in the linear region as a function of the applied gate bias for increasing stress time. The gate bias during stress was 10 V and the temperature .

Image of FIG. 2.
FIG. 2.

as a function of reciprocal temperature. The line shows that is thermally activated with . The inset shows the corresponding as a function of temperature.

Image of FIG. 3.
FIG. 3.

measured before and after (○) water vapor exposure. The continuous curves are a fit with stretched-exponential time dependence. Fitting parameters are in Table I. The inset shows the corresponding changes in the linear transfer curves measured for . The results were obtained in a device using thermal as gate dielectric and previously annealed at .

Tables

Generic image for table
Table I.

Activation energy , relaxation time , and dispersion parameter, , at room temperature for investigated transistors, as well as for organic and silicon transistors. The table contains both our data as well as literature data. Values are presented for gate-bias stress in accumulation and recovery.

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/content/aip/journal/apl/95/6/10.1063/1.3187532
2009-08-10
2014-04-23
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752b84549af89a08dbdd7fdb8b9568b5 journal.articlezxybnytfddd
Scitation: Gate-bias stress in amorphous oxide semiconductors thin-film transistors
http://aip.metastore.ingenta.com/content/aip/journal/apl/95/6/10.1063/1.3187532
10.1063/1.3187532
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