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Layout of one NW transistor consisting of six wires in parallel. The image shows an SEM picture with overlaid highlighting of source, drain and gate areas. A closeup of one single NW can be seen in the inset.
Chip surface with HL-1 cells on top. The cells form a dense monolayer appearing like a rough surface.
Extracellular recordings from two different chips showing the different signal components. The insets show ten seconds of the same recordings.
Representative extracellular recording of an HL-1 action potential with a planar FET (black: average of 57 action potentials, gray: single trace). The numbering is used in accordance to Fig. 3.
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