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(a) Schematic of the transfer characteristics of a conventional three-terminal graphene FET showing ambipolar properties. (b) Schematic of a transfer characteristic of a four-terminal ambipolar FET. The neutral point can be shifted by the back-gate input . (c) Circuit configuration of the polarity-controllable inverter using the four-terminal FET and a resistive load. The control input is added into the back gate. (d) Transfer curves of the polarity-controllable inverter at a control input of high and low.
Schematic structure of a four-terminal graphene FET with both a top gate and a back gate.
The measured drain current—top-gate voltage characteristics of the fabricated four-terminal graphene FET at room temperature, varying back-gate voltage as a parameter. The drain voltage is 0.8 V.
The measured dc voltage transfer characteristics of the fabricated polarity-controllable inverter at room temperature, varying back-gate control voltage as a parameter. The dc supply voltage is 1.2 V.
(a) Circuit configuration to test the function of the BPSK modulator. Binary digital data and carrier wave are added into two input terminals. (b) The input/output waveforms at 30 kHz. The dc supply voltage is 2.0 V. Output signal is ac coupled. Phase of output switches between two states, and , according to the level of the digital input. The inverter acts correctly as a BPSK modulator.
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