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High-gain integrated inverters based on ZnO metal-semiconductor field-effect transistor technology
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10.1063/1.3339876
/content/aip/journal/apl/96/11/10.1063/1.3339876
http://aip.metastore.ingenta.com/content/aip/journal/apl/96/11/10.1063/1.3339876

Figures

Image of FIG. 1.
FIG. 1.

Circuit of the SDFL inverter with underlying optical microscopic image of the device. The dark areas are overlaps of two contact layers for interconnects and shortcircuits. Diode can be connected to the circuit with conductive epoxy resin.

Image of FIG. 2.
FIG. 2.

Voltage transfer characteristic for the SDFL inverter S1 without level shifter (LS), with one diode and with two diodes . The operating points for inverter with LS and without LS are marked with dots and labeled with . Inset: Measured NOR-function of the SDFL inverter using as additional input .

Image of FIG. 3.
FIG. 3.

(a) Peak gain magnitude and (b) uncertainty level for the SDFL inverter S1 without level shifter (LS), with one diode and with two diodes as a function of supply voltage .

Tables

Generic image for table
Table I.

Properties of the inverter part (without level shifter) of the samples S1 and S2 (best inverters).

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/content/aip/journal/apl/96/11/10.1063/1.3339876
2010-03-15
2014-04-16
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752b84549af89a08dbdd7fdb8b9568b5 journal.articlezxybnytfddd
Scitation: High-gain integrated inverters based on ZnO metal-semiconductor field-effect transistor technology
http://aip.metastore.ingenta.com/content/aip/journal/apl/96/11/10.1063/1.3339876
10.1063/1.3339876
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