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Effects of rapid thermal annealing on reaction barrier layer/thermal-nitrided stacking gate dielectrics on n-type 4H-SiC
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10.1063/1.3367891
/content/aip/journal/apl/96/12/10.1063/1.3367891
http://aip.metastore.ingenta.com/content/aip/journal/apl/96/12/10.1063/1.3367891

Figures

Image of FIG. 1.
FIG. 1.

Typical high-frequency (1 MHz) normalized capacitance-voltage curves of (a) as-deposited and annealed samples without SiN-RBL, (b) as-deposited and annealed samples with SiN-RBL. Arrows indicate the gate voltage sweeping directions.

Image of FIG. 2.
FIG. 2.

The distributions of the interface trap density, , as a function of the energy levels between 0.2 to 0.8 eV below conduction bandedge of the dielectrics at room temperature. The error ranges on the point amount are roughly a factor 2 in the values.

Image of FIG. 3.
FIG. 3.

HR-TEM images for (a) as-deposited and (b) annealed samples with SiN-RBL, (c) as-deposited and (d) annealed samples without SiN-RBL. Arrows indicate the nanoparticles into the .

Tables

Generic image for table
Table I.

A comparison of ideal flatband voltage , measured flatband voltage , flatband voltage shift , and effective oxide charge of all samples.

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/content/aip/journal/apl/96/12/10.1063/1.3367891
2010-03-25
2014-04-25
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752b84549af89a08dbdd7fdb8b9568b5 journal.articlezxybnytfddd
Scitation: Effects of rapid thermal annealing on Al2O3/SiN reaction barrier layer/thermal-nitrided SiO2 stacking gate dielectrics on n-type 4H-SiC
http://aip.metastore.ingenta.com/content/aip/journal/apl/96/12/10.1063/1.3367891
10.1063/1.3367891
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