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Monolayer dual gate transistors with a single charge transport layer
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Image of FIG. 1.

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FIG. 1.

A schematic of the dual gate SAMFET is provided with a SEM image of a FIB cross section of the actual device below. The holes in the Teflon layer in the SEM image are an artifact caused by the high energy ions used for milling in the FIB process. The chemical structure of the self-assembling molecule is shown on the right.

Image of FIG. 2.

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FIG. 2.

Transfer characteristics for the top (above) and bottom (below) gate are presented for a drain bias of −2 V. The channel length and width are and , respectively. For both gate sweeps, the opposite gate is varied in steps of 3 V from −6 to . The inset shows the resulting threshold voltage shift vs the applied bias on the opposite gate.

Image of FIG. 3.

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FIG. 3.

(a) The drain current of the transistor is plotted vs the accumulated charge (Q) for both the bottom (solid line) and top (dashed line) gate. For the linear regime, at −2 V (the two lower curves) drain bias, the top gate yields a lower current than the bottom gate for the same induced charge. In the saturated regime, at (upper curves), both gates show the same current for equivalent charge. (b) Output curves of the top and bottom gate. For both gates, the gate voltage was varied in 5V steps from 5V to . For the top gate drain sweeps, the bottom gate bias was at and for the bottom gate drain sweeps the top gate bias was . The out curves for both gates are presented for similar drain currents by tuning the opposing gate's bias, to ease comparing the two measurements.

Image of FIG. 4.

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FIG. 4.

A TEM image of a cross section of the dual gate SAMFET. The dark field image depicts the electrode as a black line protruding from the left side of the picture. The Teflon has varying shades of gray because of the damage it received from the focused ion beam used to drill the slice from the substrate. The two arrows in the inset indicate the SAM layer, which is visible as a faint gray line on the surface of the dielectric. The layer has a thickness of , which is in good agreement with the calculated length of the molecule. The injection region for the top gate is shielded by the overhanging part of the electrode, hampering charge accumulation.


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A dual gate transistor was fabricated using a self-assembledmonolayer as the semiconductor. We show the possibility of processing a dielectric on top of the self-assembledmonolayer without deteriorating the device performance. The two gates of the transistor accumulate charges in the monomolecular transport layer and artifacts caused by the semiconductor thickness are negated. We investigate the electrical transport in a dual gate self-assembledmonolayerfield-effect transistor and present a detailed analysis of the importance of the contact geometry in monolayerfield-effect transistors.


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Scitation: Monolayer dual gate transistors with a single charge transport layer