banner image
No data available.
Please log in to see this content.
You have no subscription access to this content.
No metrics data to plot.
The attempt to load metrics for this article has failed.
The attempt to plot a graph for these metrics has failed.
Capacitor-less memory-cell fabricated on nanoscale unstrained Si layer on strained SiGe layer-on-insulator
Rent this article for
View: Figures


Image of FIG. 1.
FIG. 1.

(a) Schematic cell structure and cross sectional TEM image for the structure of unstrained Si on . The thicknesses for unstrained, strained SiGe, and BOX layers were 10 nm, 106 nm, and 175 nm, respectively. (b) characteristic curves for SOI and unstrained Si on with a Ge concentration of 8 and capacitor-less memory-cells. Drain current for three different transistor cells was compared by applying a gate bias of 1, 2, and 3 V.

Image of FIG. 2.
FIG. 2.

(a) Schematic energy-band diagram for unstrained Si on capacitor-less memory-cell at the equilibrium state. Electron affinity and energy gap of material are less than that of unstrained Si material. (b) Conduction and valence energy band-offset with a varying of Ge concentration. Valence band-offset is much more reliant on Ge concentration than the conduction band.

Image of FIG. 3.
FIG. 3.

(a) Effective mobility vs inversion charge for SOI, unstrained Si on with a concentration of 8 and 19% capacitor-less memory-cells. The effective mobility at for unstrained Si on cell is 36.1% lower than SOI cell. (b) vs Ge concentration when the drain bias was applied to 0.05 and 1 V. All are decreased with increasing drain bias because of potential-barrier lowering.

Image of FIG. 4.
FIG. 4.

(a) and potential-barrier lowering as a function of Ge concentration. decreases linearly with increasing Ge concentration but potential-barrier lowering value increases exponentially with Ge concentration. (b) Memory margin as a function of Ge concentration. It was confirmed that memory margin at the Ge concentration of is 3.2 times larger than SOI capacitor-less memory-cell.


Article metrics loading...


Full text loading...

This is a required field
Please enter a valid email address
752b84549af89a08dbdd7fdb8b9568b5 journal.articlezxybnytfddd
Scitation: Capacitor-less memory-cell fabricated on nanoscale unstrained Si layer on strained SiGe layer-on-insulator