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Gate-defined double quantum dot with integrated charge sensors realized in InGaAs/InP by incorporating a high- dielectric
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10.1063/1.3409223
/content/aip/journal/apl/96/16/10.1063/1.3409223
http://aip.metastore.ingenta.com/content/aip/journal/apl/96/16/10.1063/1.3409223
View: Figures

Figures

Image of FIG. 1.
FIG. 1.

(a) Schematic diagram showing the cross section of a device, where InGaAs/InP heterostructure, film, Ti/Au gate and cross-linked PMMA material are indicated. A negative voltage can be applied to the Ti/Au gate to deplete the 2DEG beneath. (b) Scanning electron microscope image of the central part of the device studied in this work (top view) and measurement circuit setup. The scale bar is 200 nm.

Image of FIG. 2.
FIG. 2.

Source-drain current measured for the double QD device, at a small bias of , as a function of plunger gate voltages and (a charge stability diagram). Two typical triple points are marked with a thick and a thin circle, and a few charge states are indicated by integer numbers in parentheses , where stands for the number of electrons in the left QD and the number of electrons in the right QD.

Image of FIG. 3.
FIG. 3.

Charge sensing experiment. Here, the data shown in [(a)–(c)] were measured simultaneously. (a) Transconductance (charge sensing signal) of the left QPC, (b) source-drain current measured for the double QD device under a small bias of (a charge stability diagram), and (c) transconductance (charge sensing signal) of the right QPC. In the measurements, was swept, while was stepped.

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/content/aip/journal/apl/96/16/10.1063/1.3409223
2010-04-21
2014-04-20
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752b84549af89a08dbdd7fdb8b9568b5 journal.articlezxybnytfddd
Scitation: Gate-defined double quantum dot with integrated charge sensors realized in InGaAs/InP by incorporating a high-κ dielectric
http://aip.metastore.ingenta.com/content/aip/journal/apl/96/16/10.1063/1.3409223
10.1063/1.3409223
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