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Scaling down of amorphous indium gallium zinc oxide thin film transistors on the polyethersulfone substrate employing the protection layer of parylene-C for the large-scale integration
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10.1063/1.3454775
/content/aip/journal/apl/96/24/10.1063/1.3454775
http://aip.metastore.ingenta.com/content/aip/journal/apl/96/24/10.1063/1.3454775
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Figures

Image of FIG. 1.
FIG. 1.

(a) The schematic diagram of a-IGZO TFT on the structure of /parylene-C/PES substrate. Parylene-C is used to protect PES substrate from organic solvents and acids. Also, is used as the adhesive layer. (b) Deposition process of parylene-C.

Image of FIG. 2.
FIG. 2.

(a) SEM image and (b) AFM image of the surface of parylene-C on the PES substrate. The surface roughness of the parylene-C is confirmed to be about 2 nm by AFM.

Image of FIG. 3.
FIG. 3.

(a) SEM image of patterned electrode fabricated on the parylene-C/PES substrate (inset: it is observed that electrode is detached via the hydrophobic property of parylene-C). (b) SEM image of line patterns fabricated on the /parylene-C/PES substrate.

Image of FIG. 4.
FIG. 4.

(a) Output characteristics and (b) transfer characteristics of a-IGZO TFT fabricated on the /parylene-C/PES substrate. Device is annealed at .

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/content/aip/journal/apl/96/24/10.1063/1.3454775
2010-06-16
2014-04-19
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752b84549af89a08dbdd7fdb8b9568b5 journal.articlezxybnytfddd
Scitation: Scaling down of amorphous indium gallium zinc oxide thin film transistors on the polyethersulfone substrate employing the protection layer of parylene-C for the large-scale integration
http://aip.metastore.ingenta.com/content/aip/journal/apl/96/24/10.1063/1.3454775
10.1063/1.3454775
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