1887
banner image
No data available.
Please log in to see this content.
You have no subscription access to this content.
No metrics data to plot.
The attempt to load metrics for this article has failed.
The attempt to plot a graph for these metrics has failed.
Self-aligned imprint lithography for top-gate amorphous silicon thin-film transistor fabrication
Rent:
Rent this article for
USD
10.1063/1.3457446
/content/aip/journal/apl/96/26/10.1063/1.3457446
http://aip.metastore.ingenta.com/content/aip/journal/apl/96/26/10.1063/1.3457446
View: Figures

Figures

Image of FIG. 1.
FIG. 1.

Three-level mold fabrication. Source (S) and drain (D) structure is self-aligned to the gate structure for the pattern definition of the top-gate a-Si TFT. The mold blank is a -thick layer on a glass substrate covered by 60 nm Cr. (a) First photolithography and RIE step defines the gate. (b) Second photolithography defines S and D. (c) Removal of photoresist (note that the Cr layer defines now both S/D and gate). (d) Second RIE step etches S/D and gate structures simultaneously. (e) Removal of Cr layer by wet-etching to expose final three-level mold. (f) Scanning electron microscopy image of the three levels on the mold at the S/D and gate cross-over, as indicated by the black rectangle in (e).

Image of FIG. 2.
FIG. 2.

TFT fabrication by SAIL. The top-gate a-Si TFT has Ni silicide S/D self-aligned to the gate. (a) Three-dimensional imprinted mask on top of the TFT stack after residual resist layer etch at level 0. (b) Electrical separation of TFTs by RIE. (c) Thinning of the imprint resist to expose level 2. (d) Etching of Cr layer in S/D area. (e) Removal of imprint resist and anisotropic etch. (f) Blanket deposition of Ni, silicidation step and selective removal of unreacted Ni to expose the finished TFT.

Image of FIG. 3.
FIG. 3.

Room temperature dc transfer characteristics [drain source current and gate source current vs gate source voltage measured at drain source voltages of 0.1 and 10 V] for a top-gate a-Si TFT fabricated by SAIL. Inset shows an optical micrograph of a top-gate TFT with .

Loading

Article metrics loading...

/content/aip/journal/apl/96/26/10.1063/1.3457446
2010-06-28
2014-04-17
Loading

Full text loading...

This is a required field
Please enter a valid email address
752b84549af89a08dbdd7fdb8b9568b5 journal.articlezxybnytfddd
Scitation: Self-aligned imprint lithography for top-gate amorphous silicon thin-film transistor fabrication
http://aip.metastore.ingenta.com/content/aip/journal/apl/96/26/10.1063/1.3457446
10.1063/1.3457446
SEARCH_EXPAND_ITEM