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Metal-related gate sinking due to interfacial oxygen layer in Ir/InAlN high electron mobility transistors
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10.1063/1.3458700
/content/aip/journal/apl/96/26/10.1063/1.3458700
http://aip.metastore.ingenta.com/content/aip/journal/apl/96/26/10.1063/1.3458700
View: Figures

Figures

Image of FIG. 1.
FIG. 1.

Transfer characteristics before and after annealing of (a) Ni/Au and (b) Ir/Au gate stacks.

Image of FIG. 2.
FIG. 2.

Gate capacitance measurement of Ir/Au diodes without annealing and after annealing at 400, 500, and . With increasing annealing temperature the original capacitance plateau decreases and the second plateau of the inhomogeneously sunk gate area at higher threshold voltage increases. The inset shows a schematic view of the oxygen diffusion and the gate sinking process for a fractional gate area .

Image of FIG. 3.
FIG. 3.

TEM image and corresponding EELS oxygen and iridium map of the 2 nm barrier with Ir/Au metallization after annealing at . Bright areas in the EELS images correspond to the mapped element.

Image of FIG. 4.
FIG. 4.

Drain current and transconductance characteristic of a 500-nm-long Ir/Au gate device after annealing.

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/content/aip/journal/apl/96/26/10.1063/1.3458700
2010-07-02
2014-04-23
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752b84549af89a08dbdd7fdb8b9568b5 journal.articlezxybnytfddd
Scitation: Metal-related gate sinking due to interfacial oxygen layer in Ir/InAlN high electron mobility transistors
http://aip.metastore.ingenta.com/content/aip/journal/apl/96/26/10.1063/1.3458700
10.1063/1.3458700
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