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Transfer characteristics before and after annealing of (a) Ni/Au and (b) Ir/Au gate stacks.
Gate capacitance measurement of Ir/Au diodes without annealing and after annealing at 400, 500, and . With increasing annealing temperature the original capacitance plateau decreases and the second plateau of the inhomogeneously sunk gate area at higher threshold voltage increases. The inset shows a schematic view of the oxygen diffusion and the gate sinking process for a fractional gate area .
TEM image and corresponding EELS oxygen and iridium map of the 2 nm barrier with Ir/Au metallization after annealing at . Bright areas in the EELS images correspond to the mapped element.
Drain current and transconductance characteristic of a 500-nm-long Ir/Au gate device after annealing.
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