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Single-gate accumulation-mode InGaAs quantum dot with a vertically integrated charge sensor
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View: Figures


Image of FIG. 1.
FIG. 1.

(a) A schematic diagram showing the layer structure and gate geometry for our devices. Two quantum wells surrounded by form the confining layers for both the quantum dot (in the upper well) and the readout channel (lower well). (b) A view from above showing the air-bridged gate electrode, the QPC, and the current path. (c) Scanning electron microscope images from representative devices.

Image of FIG. 2.
FIG. 2.

Differential transconductance obtained by recording the in-phase component of the QPC current due to a 17.7 Hz, excitation added to . Dot transitions are observed as sloping lines when plotted by versus QPC bias . The slight negative slope to the dot transitions is a result of the capacitive coupling between the dot and the metal QPC gates. Dot occupancy for the first ten electrons is labeled in white.

Image of FIG. 3.
FIG. 3.

(a) Representative time trace of the change in QPC current as the dot experiences thermally induced loading and unloading events, known as random telegraph signal. The gate bias, , was nominally centered on the electron transition. (b) Average lifetimes for loading (, blue circles) and unloading (, black crosses) the first dot state as a function of . The solid lines are fits of the data to the formulas in the text.


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752b84549af89a08dbdd7fdb8b9568b5 journal.articlezxybnytfddd
Scitation: Single-gate accumulation-mode InGaAs quantum dot with a vertically integrated charge sensor