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Insight into the performance enhancement of double-gated polycrystalline silicon thin-film transistors with ultrathin channel
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10.1063/1.3327336
/content/aip/journal/apl/96/7/10.1063/1.3327336
http://aip.metastore.ingenta.com/content/aip/journal/apl/96/7/10.1063/1.3327336
View: Figures

Figures

Image of FIG. 1.
FIG. 1.

Simplified 2D schematic illustration of the device applied in 2D TCAD simulation.

Image of FIG. 2.
FIG. 2.

(a) Transfer and (b) output characteristics of the device with poly-Si channel , gate , and gate under DG and SG modes of operation. Both experimental (solid and dashed lines) and simulated (symbols) data are shown for comparison. In (b), the drain current of SG mode is multiplied by 2 for fair comparison with that of DG mode.

Image of FIG. 3.
FIG. 3.

(a) Extracted as a function of gate voltage for the device characterized in Fig. 2. The inset shows some of the vs T curves for extracting . DG mode shows reduced as compared with the SG mode. (b) The simulated values at , 3, and 5 nm.

Image of FIG. 4.
FIG. 4.

Comparisons of experimental and simulated TEF under DG and SG operations.

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/content/aip/journal/apl/96/7/10.1063/1.3327336
2010-02-18
2014-04-19
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752b84549af89a08dbdd7fdb8b9568b5 journal.articlezxybnytfddd
Scitation: Insight into the performance enhancement of double-gated polycrystalline silicon thin-film transistors with ultrathin channel
http://aip.metastore.ingenta.com/content/aip/journal/apl/96/7/10.1063/1.3327336
10.1063/1.3327336
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