Full text loading...
(a) characteristics of a p-FET strained by the DLC liner stressor with , measured at 26, 76, and . is extracted at constant current of . decreases with increasing temperature. (b) DIBL of the unstrained and strained P-FETs as a function of . DIBL is defined to be the change in threshold voltage per unit change in drain bias. At each gate length, DIBL for both groups of transistors are similar. The dispersion or scatter in data is due to device-to-device variation introduced during fabrication.
(a) Saturation threshold voltage and (b) normalized change in saturation drive current as functions of characterization temperature for a p-FET with DLC liner stressor. The gate length of the p-FET is 90 nm. Linear regression was performed for the measured data, giving best-fit lines with slopes denoted by and in (a) and (b), respectively.
(a) Backscattering ratio of both the unstrained and DLC stressed p-FETs vs DIBL. (b) Ballistic efficiency of both the control and DLC stressed p-FETs vs DIBL. DIBL was measured at room temperature. For P-FETs with the DLC liner stressor, obvious degradation of and could be observed.
(a) Hole injection velocity is significantly increased for transistors with DLC liner stressor. (b) The percentage increase in hole injection velocity is plotted against the drive current enhancement. The increase in hole injection velocity more than compensates for the reduction in , giving a net increase in . The and data were obtained from transistor data measured in the range of 25 to .
Article metrics loading...