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High performance atomic-layer-deposited -on-insulator p-channel metal-oxide-semiconductor field-effect transistor with thermally grown as interfacial passivation layer
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10.1063/1.3462303
/content/aip/journal/apl/97/1/10.1063/1.3462303
http://aip.metastore.ingenta.com/content/aip/journal/apl/97/1/10.1063/1.3462303
View: Figures

Figures

Image of FIG. 1.
FIG. 1.

(a) Cross section schematic view of ALD PMOSFET with passivation layer. (b) Output characteristics of a typical channel length device with gate voltage from 0 to −5 V.

Image of FIG. 2.
FIG. 2.

Comparison of normalized drain current at for devices with or without thin interfacial layer.

Image of FIG. 3.
FIG. 3.

(a) Temperature dependent transfer characteristics for a gate length PMOSFET when drain voltage is biased at −50 mV. (b) Effective mobility vs inversion charge density for devices with and without interfacial layer.

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/content/aip/journal/apl/97/1/10.1063/1.3462303
2010-07-08
2014-04-16
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752b84549af89a08dbdd7fdb8b9568b5 journal.articlezxybnytfddd
Scitation: High performance atomic-layer-deposited LaLuO3/Ge-on-insulator p-channel metal-oxide-semiconductor field-effect transistor with thermally grown GeO2 as interfacial passivation layer
http://aip.metastore.ingenta.com/content/aip/journal/apl/97/1/10.1063/1.3462303
10.1063/1.3462303
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