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Diagram of the final device structure (not to scale but with important dimensions indicated).
(a) SEM image of a single nanoline ( linewidth) transitioning between the Ti pad and the channel, taken before ICP etch (stage tilt 30°). (b) HRTEM image of a cross section of the device channel. The a-Si:H nanowire shown is approximately 24 nm wide and 13 nm tall (single e-beam pass), and is completely surrounded by with a crystalline silicon substrate beneath.
I-V characteristics of nanowire devices with 51 nm nanowire width (produced by two e-beam passes). Channel length is . Transfer characteristics (log scale) are shown for (a) single nanowire and (c) 40 nanowire array with 500 nm pitch. Output characteristics of the same devices are shown in (b) and (d), respectively.
(a) Gate voltage at peak transconductance is similar to threshold voltage and is shown as a function of effective channel width. (b) Subthreshold swing and peak field-effect mobility improve as effective channel width is reduced. Both figures are for devices.
On-current vs. effective channel width of nanowire devices. A linear trend is observed within error of the nanowire linewidth caused by imperfect stage leveling and beam current variations. Also, the extrapolated line toward zero effective width crosses the -axis very near zero current. The inset shows the trend for single nanowire devices (very small effective width).
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