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Effects of back interface trap states on the fully depleted strained-silicon-on-insulator capacitorless single transistor dynamic random access memory cells
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10.1063/1.3494262
/content/aip/journal/apl/97/15/10.1063/1.3494262
http://aip.metastore.ingenta.com/content/aip/journal/apl/97/15/10.1063/1.3494262

Figures

Image of FIG. 1.
FIG. 1.

Schematic diagram of (a) BG MOSFET and (b) 1T-DRAM devices fabricated on the sSOI substrate.

Image of FIG. 2.
FIG. 2.

Cross-sectional TEM images of FD sSOI substrate.

Image of FIG. 3.
FIG. 3.

Dependence of drain current vs backgate voltage curves of FD sSOI BG MOSFET on the RTA temperatures. , .

Image of FIG. 4.
FIG. 4.

Current-voltage characteristics of FD sSOI capacitorless 1T-DRAM cells: (a) transfer characteristics and (b) output characteristics . .

Image of FIG. 5.
FIG. 5.

Sensing margin of current difference between “1” and “0” states of FD sSOI 1T-DRAM ( for write “1,” for read, for write “0” operation. , , and ).

Tables

Generic image for table
Table I.

Relationship of sensing margin and retention time of FD sSOI 1T-DRAM to back interface trap density.

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/content/aip/journal/apl/97/15/10.1063/1.3494262
2010-10-12
2014-04-16
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752b84549af89a08dbdd7fdb8b9568b5 journal.articlezxybnytfddd
Scitation: Effects of back interface trap states on the fully depleted strained-silicon-on-insulator capacitorless single transistor dynamic random access memory cells
http://aip.metastore.ingenta.com/content/aip/journal/apl/97/15/10.1063/1.3494262
10.1063/1.3494262
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