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Overlapping-gate architecture for silicon Hall bar field-effect transistors in the low electron density regime
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10.1063/1.3501136
/content/aip/journal/apl/97/15/10.1063/1.3501136
http://aip.metastore.ingenta.com/content/aip/journal/apl/97/15/10.1063/1.3501136
View: Figures

Figures

Image of FIG. 1.
FIG. 1.

Scanning electron micrographs of the MOSFET device architectures studied. (a) Photolithography defined Hall bar with a single gate. (b) EBL defined Hall bar with overlapping-gate architecture. (c) Zoom-in of panel (b) showing the area where the channel gate is electrically insulated from the lead gates by a thin layer of aluminum oxide .

Image of FIG. 2.
FIG. 2.

(a) Control of the contact resistance in the overlapping-gate Hall bar MOSFET (EBL fabricated device). Here only the channel gate voltage is swept as the voltage of the lead gates is increased stepwise from to 1.0 V. (b) Four-terminal device resistance as a function of the lead gate voltage.

Image of FIG. 3.
FIG. 3.

Device resistance (a) and electron density (b) as function of (channel) gate voltage for the two device architectures studied.

Image of FIG. 4.
FIG. 4.

Mobility vs electron density. Note that with the EBL device one can measure at much lower densities as compared to the PHOTO device.

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/content/aip/journal/apl/97/15/10.1063/1.3501136
2010-10-11
2014-04-16
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752b84549af89a08dbdd7fdb8b9568b5 journal.articlezxybnytfddd
Scitation: Overlapping-gate architecture for silicon Hall bar field-effect transistors in the low electron density regime
http://aip.metastore.ingenta.com/content/aip/journal/apl/97/15/10.1063/1.3501136
10.1063/1.3501136
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