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The investigation of charge loss mechanism in a two-bit wrapped-gate nitride storage nonvolatile memory
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10.1063/1.3508956
/content/aip/journal/apl/97/18/10.1063/1.3508956
http://aip.metastore.ingenta.com/content/aip/journal/apl/97/18/10.1063/1.3508956

Figures

Image of FIG. 1.
FIG. 1.

The device structure and the simulation results of the electric potential and lateral electric field under the programming conditions, , , , and .

Image of FIG. 2.
FIG. 2.

(a) The endurance and (b) the retention loss at baking of the wrapped-gate device after by using SSI programming and BBHH erasing with bias conditions listed in Table I.

Image of FIG. 3.
FIG. 3.

(a) The schematic set-up of the operating connections and (b) the input pulse waveform applying to the bulk, . (c) The measured waveform (circles) from the source or drain terminal, under the applying pulse (solid line). (d) The respective locations of the injected electrons and holes under the word-gate region and near the drain, where the ONO storage layer is underneath the word-gate.

Image of FIG. 4.
FIG. 4.

(a) The endurance and (b) the retention tests at baking temperature of the wrapped-gate device after by using SSI programming and STHH erasing with bias conditions listed in Table I.

Tables

Generic image for table
Table I.

The programming and erasing bias conditions used in this work.

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/content/aip/journal/apl/97/18/10.1063/1.3508956
2010-11-05
2014-04-24
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752b84549af89a08dbdd7fdb8b9568b5 journal.articlezxybnytfddd
Scitation: The investigation of charge loss mechanism in a two-bit wrapped-gate nitride storage nonvolatile memory
http://aip.metastore.ingenta.com/content/aip/journal/apl/97/18/10.1063/1.3508956
10.1063/1.3508956
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