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The device structure and the simulation results of the electric potential and lateral electric field under the programming conditions, , , , and .
(a) The endurance and (b) the retention loss at baking of the wrapped-gate device after by using SSI programming and BBHH erasing with bias conditions listed in Table I.
(a) The schematic set-up of the operating connections and (b) the input pulse waveform applying to the bulk, . (c) The measured waveform (circles) from the source or drain terminal, under the applying pulse (solid line). (d) The respective locations of the injected electrons and holes under the word-gate region and near the drain, where the ONO storage layer is underneath the word-gate.
(a) The endurance and (b) the retention tests at baking temperature of the wrapped-gate device after by using SSI programming and STHH erasing with bias conditions listed in Table I.
The programming and erasing bias conditions used in this work.
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