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Nanoscale gadolinium oxide capping layers on compositionally variant gate dielectrics
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View: Figures


Image of FIG. 1.
FIG. 1.

C-V curves of devices with nearly the same EOT showing the gradual shift in C-V curve with in the gate dielectric. The dotted line is for a device without the capping layer. The inset shows a TEM x-section of the stack.

Image of FIG. 2.
FIG. 2.

-EOT plots showing the shift in over a range of EOTs for samples (a) without capping layer and for samples with 1.0 nm capping layer where gate dielectric contains (b) 0% , (c) 60% , and (d) 100% . Negligible interfacial fixed charges are obtained.

Image of FIG. 3.
FIG. 3.

Extracted effective work function (EWF) values as a function of in the gate dielectric where all devices had 1.0 nm capping layer. The magnitude of the increase in EWF is marked by , , and .

Image of FIG. 4.
FIG. 4.

EELS chemical profile recorded across containing gate stacks. The results show the Gd element signal variation with depth in and stacks. The Gd has diffused toward the Si interface, but not into TaN. Furthermore, the normalized concentration plot shows that more Gd has diffused in the case of than .

Image of FIG. 5.
FIG. 5.

Results showing the shift as a function of in the gate dielectric and gate dielectric density. The inset shows the impact of maximum thermal budget on shift for 60% dielectric.


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752b84549af89a08dbdd7fdb8b9568b5 journal.articlezxybnytfddd
Scitation: Nanoscale gadolinium oxide capping layers on compositionally variant gate dielectrics