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Cross-sections of two strained nFET splits: (a) nFET with conventional Si:C S/D and (b) nFET with channel proximate (CP) Si:C S/D. For both splits, multiple-energy carbon implant ( at 2.5 keV, at 5.5 keV, and at 12 keV) were used to achieve a uniform C concentration of 1.5 at. % in the top of the S/D regions. Source-to-drain direction is along the  crystal direction. (c) Parasitic resistance was extracted using the method in Ref. 24. For each split, four samples were characterized and the standard deviation is plotted as error bars. Carbon in the S/D increases . (d) Diagram showing the presence of parasitic source resistance , drain resistance , and gate resistance in an nFET. Applied or extrinsic voltages are denoted by and , while , , and are the intrinsic terminal voltages of an nFET without parasitic resistances (in dashed box).
(a) CP Si:C S/D nFETs have lower ratio than Si:C S/D nFETs. Standard deviation of the ratio at each is plotted as error bars. The degradation in ratio is attributed to the reduction in possibly caused by the diffusion of carbon into the strained silicon channel as a result of the increased proximity between the Si:C S/D stressors and the channel for CP Si:C S/D nFETs. (b) Reduction in for CP Si:C S/D nFETs contributed to an increase in for CP Si:C S/D nFETs as compared to Si:C S/D nFETs.
is lower in nFETs with CP Si:C S/D than in nFETs with Si:C S/D. This indicates that placing the Si:C S/D closer to the channel increases carrier backscattering in the channel region near the source.
(a) Significant increase in accounts for the enhancement observed in CP Si:C S/D nFETs over Si:C S/D nFETs. enhancement is obtained by comparing the mean of nFETs with CP Si:C S/D against that of nFETs with conventional Si:C S/D at the same gate length. (b) Correlation of and enhancement showing that the percentage mobility improvement is approximately two times the enhancement.
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