Analysis of InAs vertical and lateral band-to-band tunneling transistors: Leveraging vertical tunneling for improved performance
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Schematic of the simulated devices (a) lateral InAs TFET and (b) vertical InAs TFET with a heavily doped pocket (halo) in the gate-source overlap region. The doping profiles in all our simulations are abrupt with a source and drain doping of and , respectively. The asymmetry in doping concentrations is motivated by the lower conduction band density of states in InAs and the need to suppress ambipolar conduction. In case of vertical TFET, we use a pocket doping of . Although the channel region is intrinsic, we use an n-type doping of to account for unintentional doping arising due to defects. A 1.2 nm gate dielectric with is used. The length of source and drain in our simulations is 20 nm each with a 10 nm overlap on the source side in case of vertical TFET. For 10 nm thick body, the pocket is 3.6 nm deep while for a body thickness of 6 nm, we use a pocket depth of 2.4 nm. The crystallographic direction is assumed to be (100) for transport and the body is confined along (001) direction. Also, the difference in workfunction between semiconductor and gate metal— is assumed to be zero.
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(a) characteristics at for lateral and vertical TFETs for channel length . The markers indicate values from simulation and lines, the interpolated curve. (b) The energy band diagrams in a 10 nm thick vertical TFET along the lateral direction near the semiconductor-dielectric interface for following different gate voltages: from 0.15 V to 0.45 V in steps of 0.1 V. (c) The energy band diagrams along the body thickness in the middle of the pocket for same gate voltages as in (b). (d) Similar band diagrams for a 6 nm thick device with no back-gate for following two different gate voltages: 0.8 V and 1.1 V. From (a), we can see that the vertical TFETs have smaller OFF state currents and larger ON currents than their lateral counterparts. The vertical TFETs also have steeper subthreshold swing. While (c) shows band overlap for the 10 nm case and (d) does not show any overlap even at high gate voltages (1.1 V). Note that in (d), a single gate geometry has been chosen to maximize the possibility of band overlap as a double gate structure could further degrade the band overlap.
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(a) characteristics at for vertical TFETs for three different channel lengths −10, 20, and 30 nm showing the scaling behavior. (b) Similar curves for lateral TFETs. From (a) and (b), it is evident that TFETs show poor scalability and show less than 60 mV/decade subthreshold slope only for longer channel lengths. (c) LDOS on a logarithmic scale for vertical TFET with at near the semiconductor-dielectric interface showing large penetration of tunneling states in the channel owing to smaller effective mass of InAs. (d) Energy resolved current density for lateral TFET with different channel lengths at showing significant current flowing due to tunneling through the channel for shorter devices, thereby limiting the maximum subthreshold slope and minimum OFF current.
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